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19-3484; Rev 0; 11/04
Integrated Powerline Digital Transceiver
General Description
The MAX2986 powerline transceiver utilizes state-of-theart CMOS design techniques to deliver the highest level of performance and flexibility. This highly integrated design combines the media access control layer (MAC) and the physical layer (PHY) in a single chip. The MAX2986 digital baseband and its companion device, the MAX2980* analog front-end (AFE), offer a complete high-speed powerline communication solution that is fully compatible with third-party HomePlug(R) 1.0 devices. The MAX2986 digital transceiver utilizes Maxim's advanced OFDM powerline engine with adaptive data rates up to 14Mbps. The MAX2986's open architecture allows extensive programmability, feature enhancement capability, and improved testability in the MAC for optimum performance. Hence, this device is aimed at applications such as local area networks (LANs), audio, voice, home automation, industrial automation, and broadband-over-powerline (BPL), as well as spectral shaping and tone notching capability, providing an unparalleled level of flexibility to conform to the disparate local regulatory bodies. Maxim's modified OFDM technique allows shaping of power spectral density of the transmitted signal arbitrarily to accommodate any desired subcarrier set and to place spectral nulls at any unwanted frequency location. The automatic channel adaptation and interference rejection features of the MAX2986 guarantee outstanding performance. Privacy is provided by a 56-bit DES encryption with key management. The MAX2986 operates with IEEE 802.03 standard media independent interface (MII), reduced media independent interface (rMII), buffered FIFO data communication, IEEE 802.03 compatible 10/100 Ethernet MAC, or USB 1.1 interfaces. These interfaces allow the MAX2986 to be paired with almost any data communication devices to use in a variety of information appliances. Up to 14Mbps Data Rate 4.49MHz to 20.7MHz Frequency Band Upgradeable/Programmable MAC Spectral Shaping Including Bandwidth and Notching Capability Programmable Preamble Access to Application Protocol Interface (API) 128kB Internal SRAM JTAG Interface Large Bridge Table: Up to 512 Addresses 56-Bit DES Encryption with Key Management for Secure Communication Advanced Narrowband Interference Rejection Circuitry OFDM-Based PHY 84 Carriers Automatic Channel Adaptation FEC (Forward Error Correction) DQPSK, DBPSK, ROBO On-Chip Interfaces 10/100 Ethernet USB 1.1 MII/rMII/FIFO Compatible with HomePlug 1.0 Standard
Features
Single-Chip Powerline Networking Transceiver
MAX2986
Applications
Broadband-Over-Powerline Local Area Networks (LANs) Multimedia-Over-Powerline Voice-Over-Powerline Industrial Automation (Remote Monitoring and Control) Home Automation Security and Safety
PART MAX2986CXV
Ordering Information
TEMP RANGE 0C to +70C PIN-PACKAGE 144 CSBGA
*Future product--contact factory for availability. HomePlug is a registered trademark of HomePlug Powerline Alliance, Inc. Pin Configuration and Typical Application Circuit appear at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Integrated Powerline Digital Transceiver MAX2986
ABSOLUTE MAXIMUM RATINGS
VDD33 to DGND .....................................................-0.5V to +4.6V VDD18 to DGND, DVDD to DVSS ............................-0.5V to +2.5V AVDD to AVSS ........................................................-0.5V to +2.5V All Other Input Pins...................................................-0.5V to +6V All Other Output Pins.............................................-0.5V to +4.6V
CAUTION! ESD SENSITIVE DEVICE Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Continuous Power Dissipation (TA = +70C) 144-Bump CSBGA (derate 25.6mW/C at +70C) .........2045mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C
ELECTRICAL CHARACTERISTICS
(VDD33 = +3.3V, VDD18 = DVDD = AVDD = +1.8V, AVSS = DVSS = DGND = 0, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Digital-Supply Voltage Range Core-Supply Voltage Range Digital I/O Supply Current Core Supply Current PLL Supply Current Output-Voltage High Output-Voltage Low Input High Voltage Input Low Voltage Input Leakage Current SYMBOL VDD33 VDD18 IDD33 IDD18 IPLL VOH VOL VIH VIL ILEAK UARTTXD, AFEFRZ, AFEPDRX, AFEREN, AFERESET, AFETXEN, ETHMDC, ETHTXD[0], ETHTXD[1], ETHTXD[2], ETHTXD[3], ETHTXEN, ETHTXER, JRTCK, MIICRS, MIIRXDV, MIIRXER AFECLK JTDO (tri-state port) UARTTXD, AFEFRZ, AFEPDRX, AFEREN, AFERESET, AFETXEN, ETHMDC, ETHTXD[0], ETHTXD[1], ETHTXD[2], ETHTXD[3], ETHTXEN, ETHTXER, JRTCK, MIICRS, MIIRXDV, MIIRXER AFECLK JTDO (tri-state port) 2.0 -0.3 -80 2.3 0.5 5.5 +0.8 +80 CONDITIONS Guaranteed by PSRR MIN 3.0 1.62 TYP 3.3 1.8 41 426 8 MAX 3.6 1.98 UNITS V V mA mA mA V V V V A
POWER-SUPPLY CHARACTERISTICS
LOGIC INPUT CHARACTERISTICS
4 mA 16 4
Output High Current
IOH
4 mA 16 4
Output Low Current
IOL
2
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Integrated Powerline Digital Transceiver
Pin Description
BUMP A1, L2 A2, L3 A3, M1 NAME DVDD DVSS AVDD PLL Ground 1.8V PLL Analog Power Supply. Bypass to AVSS with a 100nF capacitor as close to the pin as possible. General-Purpose Input/Output 2. GPIO[2] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[2] if not used. The MAX2986 software uses GPIO[2] to control external USB circuit. General-Purpose Input/Output 22. GPIO[22] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[22] if not used. The MAX2986 MAC uses GPIO[22] for AFE interface link status LED (output) and boot pin bit 1 (input). FUNCTION 1.8V PLL Digital Power Supply. Bypass to DVSS with a 100nF capacitor as close to the pin as possible.
MAX2986
A4
GPIO[2]
A5
GPIO[22]
A6, C1, C13, F12, J1, L1, L4, L10, M13 A7 A8
VDD33
3.3V Digital Power Supply. Bypass to DGND with a 100nF capacitor as close to the pin as possible. General-Purpose Input/Output 17. GPIO[17] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[17] if not used. General-Purpose Input/Output 14. GPIO[14] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[14] if not used. General-Purpose Input/Output 11. GPIO[11] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[11] if not used. The MAX2986 MAC uses GPIO[11] as processor ID, bit 0 (input). General-Purpose Input/Output 9. GPIO[9] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[9] if not used. The MAX2986 MAC uses GPIO[9] as serial data in nonvolatile memory interface. General-Purpose Input/Output 7. GPIO[7] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[7] if not used. The MAX2986 MAC uses GPIO[7] as AFE interface powerdown signal. General-Purpose Input/Output 5. GPIO[5] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[5] if not used. The MAX2986 MAC uses GPIO[5] as AFE interface serial data signal. General-Purpose Input/Output 4. GPIO[4] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[4] if not used. The MAX2986 MAC uses GPIO[4] for AFE interface serial clock signal (output) and upper layer interface bit 0 (input).
GPIO[17] GPIO[14]
A9
GPIO[11]
A10
GPIO[9]
A11
GPIO[7]
A12
GPIO[5]
A13 B1, C2, D4- D9, E3, E11, E12, E13, F4, F13, K5, K6, K8, K9, M10, M11, N1, N6 B2, M2 B3
GPIO[4]
DGND
Digital Ground
AVSS GPIO[0]
Analog PLL Ground General-Purpose Input/Output 0. GPIO[0] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[0] if not used.
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3
Integrated Powerline Digital Transceiver MAX2986
Pin Description (continued)
BUMP B4 B5 B6 NAME GPIO[3] USBD+ GPIO[21] FUNCTION General-Purpose Input/Output 3. GPIO[3] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[3] if not used. USB Interface Data Signal (+) General-Purpose Input/Output 21. GPIO[21] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[21] if not used. The MAX2986 MAC uses GPIO[21] for AFE interface collision LED (output) and boot pin bit 0 (input). General-Purpose Input/Output 18. GPIO[18] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[18] if not used. General-Purpose Input/Output 15. GPIO[15] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[15] if not used. General-Purpose Input/Output 12. GPIO[12] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[12] if not used. The MAX2986 MAC uses GPIO[12] as processor ID, bit 1 (input). General-Purpose Input/Output 10. GPIO[10] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[10] if not used. The MAX2986 MAC uses GPIO[10] as nonvolatile memory chip-select signal (output) and nonvolatile memory type, bit 1 (input). General-Purpose Input/Output 8. GPIO[8] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[8] if not used. The MAX2986 MAC uses GPIO[8] as nonvolatile memory serial clock signal (output) and nonvolatile memory type, bit 0 (input). General-Purpose Input/Output 6. GPIO[6] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[6] if not used. The MAX2986 MAC uses GPIO[6] as AFE interface serial write signal (output) and upper layer interface bit 1 (input).
B7 B8
GPIO[18] GPIO[15]
B9
GPIO[12]
B10
GPIO[10]
B11
GPIO[8]
B12
GPIO[6]
B13, D1, D11, D12, D13, E1, K4, M12 C3
N.C.
No Connection. Must be left unconnected (floating output). General-Purpose Input/Output 1. GPIO[1] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[1] if not used. General-Purpose Input/Output 23. GPIO[23] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[23] if not used. The MAX2986 MAC uses GPIO[23] for AFE interface link activity LED (output) and boot pin bit 2 (input). USB Interface Data Signal (-) General-Purpose Input/Output 20. GPIO[20] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[20] if not used. General-Purpose Input/Output 19. GPIO[19] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[19] if not used. General-Purpose Input/Output 16. GPIO[16] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[16] if not used. General-Purpose Input/Output 13. GPIO[13] is in tri-state during boot up. Connect a 100k pullup or pulldown resistor to GPIO[13] if not used. The MAX2986 MAC uses GPIO[13] as processor ID, bit 2 (input).
GPIO[1]
C4 C5 C6 C7 C8
GPIO[23] USBDGPIO[20] GPIO[19] GPIO[16]
C9
GPIO[13]
4
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Integrated Powerline Digital Transceiver
Pin Description (continued)
BUMP C10, D10, E10, F10, G10, J10, K10 C11 C12 D2 D3 E2 E4 F1 F2 F3 F11 G1 G2 G3 G4 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J2 J3 J4 J11 J12 J13 K1 K2 K3 K7 K11 K12 NAME VDD18 JTMS JTDI USBRESET RESET JRTCK AFEFRZ AFETXEN XIN XOUT MIITXEN AFERESET FUNCTION +1.8V Digital Power Supply. Bypass to DGND with a 100nF capacitor as close to the pin as possible. JTAG Test Mode Select JTAG Test Data Input Active-Low USB Reset Signal. Connect to RESET. Asynchronous, Active-Low Reset Input JTAG Return Test Clock Analog Front-End Carrier Sense Indicator Analog Front-End Transmitter Enable Output Crystal Input (30MHz) Crystal Output MII Transmit Enable AFE Reset
MAX2986
AFEDAD[0] Analog Front-End DAC/ADC Input/Output 0 Interface AFEDAD[1] Analog Front-End DAC/ADC Input/Output 1 Interface AFEDAD[2] Analog Front-End DAC/ADC Input/Output 2 Interface JTDO JTRST JTCK JTAG Test Data Output Active-Low JTAG Test Reset JTAG Test Clock
AFEDAD[3] Analog Front-End DAC/ADC Input/Output 3 Interface AFEDAD[4] Analog Front-End DAC/ADC Input/Output 4 Interface AFEDAD[5] Analog Front-End DAC/ADC Input/Output 5 Interface AFEDAD[6] Analog Front-End DAC/ADC Input/Output 6 Interface MIIRXDV BUFRD BUFCS BUFWR MII Receive Data Valid Active-Low FIFO Read Enable Active-Low FIFO Chip Enable Active-Low FIFO Write Enable
AFEDAD[7] Analog Front-End DAC/ADC Input/Output 7 Interface AFEDAD[8] Analog Front-End DAC/ADC Input/Output 8 Interface AFEDAD[9] Analog Front-End DAC/ADC Input/Output 9 Interface MIIMDC MIIDAT[7] MIIDAT[5] AFECLK AFEREN AFEPDRX UARTTXD MIICRS MIIDAT[6] MII Management Data Clock MII/FIFO Transmit/Receive Data [7] MII/FIFO Transmit/Receive Data [5] 50MHz AFE Clock Analog Front-End Read Enable Output AFE Receiver Power-Down UART Transmit MII Carrier Sense MII/FIFO Transmit/Receive Data [6]
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5
Integrated Powerline Digital Transceiver MAX2986
Pin Description (continued)
BUMP K13 L5 L6 L7 L8 L9 L11 L12 L13 M3 M4 M5 M6 M7 M8 M9 N2 N3 N4 N5 N7 N8 N9 N10 N11 N12 N13 NAME MIIMDIO UARTRXD ETHTXD[3] ETHTXD[2] ETHTXCLK MIIRXER MIIDAT[4] MIIDAT[0] ETHMDC MII Management Data UART Receive Ethernet MII Transmit Data Bit 3 Ethernet MII Transmit Data Bit 2 Ethernet MII Transmit Clock MII Receive-Error Indicator MII/FIFO Transmit/Receive Data [4] MII/FIFO Transmit/Receive Data [0] Ethernet Management Data Interface Clock ETHRXD[1] Ethernet MII Receive Data Bit 1 FUNCTION
ETHRXCLK Ethernet MII Receive Clock ETHRXD[2] Ethernet MII Receive Data Bit 2 ETHRXD[0] Ethernet MII Receive Data Bit 0 ETHRXDV ETHTXD[0] ETHTXEN ETHCOL ETHCRS ETHMDIO ETHRXER ETHTXD[1] ETHTXER MIICLK MIIDAT[3] MIIDAT[2] MIIDAT[1] Ethernet MII Receive Data Valid Ethernet MII Transmit Data Bit 0 Ethernet MII Transmit Enable Ethernet MII Collision Ethernet MII Carrier Sense Ethernet Management Data Input/Output Ethernet MII Receive Error Ethernet MII Transmit Data Bit 1 Ethernet MII Transmit Error MII Clock MII/FIFO Transmit/Receive Data [3] MII/FIFO Transmit/Receive Data [2] MII/FIFO Transmit/Receive Data [1]
ETHRXD[3] Ethernet MII Receive Data Bit 3
6
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Integrated Powerline Digital Transceiver MAX2986
JTMS, JTDO, JTDI JTRSTN, JTCK
XIN XOUT RESET
PLL 1 PLL 2 ON-CHIP CONTROLLER RAM ENCRYPTION ENGINE
JTAG
I-ITCM
D-ITCM MAX2986 AFETXEN AFERESET AFEDAD0-9 AFECLK AFEREN AFEPDRX AFEFRZ
I-CACHE D-CACHE ARM946TM PROCESSOR (MAC SOFTWARE)
DSP ENGINE
ON-CHIP CONTROLLER ROM DMA ENGINE UARTRXD UARTTXD UART
AFE REGISTER INTERFACE
USB CONTROLLER
USBDUSBD+ USBRESET
TIMERS
ADDRESS SEARCH ENGINE
INTERRUPT CONTROLLER
ETHERNET MAC
MII/rMII FIFO
GPIO
ETHCOL, ETHMDC, ETHCRS, ETHRXCLK, ETHMDIO, ETHRXD0-3, ETHTXD0-3, ETHRXDV, ETHRXER, ETHTXCLK, ETHTXEN, ETHTXER
MIIRXDV, MIICLK MIITXEN, MIIMDC MIICRS, MIIRXER MIIDAT0-7, MIIMDIO BUFRD, BUFCS BUFWR
GPIO0-23
Figure 1. MAX2986 Functional Diagram
DATA
EXTERNAL HOST
MAX2986 MAC/PHY
MAX2980 AFE
POWERLINE COUPLER
Figure 2. Powerline Chipset System Block Diagram
Detailed Description
The MAX2986 powerline transceiver IC is a state-of-theart CMOS device, which delivers high performance at reduced cost. This highly integrated design combines the MAC layer with the PHY layer in a single chipset. The MAX2986 and the companion device, the MAX2980 AFE, form a complete HomePlug-compatible solution with a substantially reduced system cost.
ARM is a registered trademark of ARM Ltd.
MII/rMII/FIFO Interface
The MII/RMII/FIFO block is the interface layer of the MAX2986 transceiver. This layer is designed to operate with IEEE 802.3 standard MII, rMII, or any other devices using the FIFO interface. The interface is a data channel that transfers data in packets, with flow controlled by the carrier sense (MIICRS) signal. This signal controls the half-duplex transmission between the external host and the MAC. While a frame reception is in progress, (MIICRS and
7
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Integrated Powerline Digital Transceiver
MIIRXDV are high), the external host must wait until the completion of reception and the deassertion of MIICRS before starting a transmission. When sending two consecutive frames, the minimum time the external host needs to wait is the one-frame transfer time plus an interframe gap. Note: For information such as signal timing characteristics and electrical characteristics, refer to the IEEE 802.3u. Note: The MII signals MIICOL and MIITXER are not used, as the powerline networking device is able to detect and manage all transmission failures. The signals MIITXCLK and MIIRXCLK have the same source and are referred to as MIICLK in this document. In MII mode, the data is transferred synchronously with a 2.5MHz/25MHz clock. Data transmission in MII is in
MAX2986
nibble format so the data transmission rate is 10Mbps/100Mbps. In rMII mode, the data is transferred synchronously with a 5MHz/50MHz clock. Data transmission in MII is in 2-bit format so the data transmission rate is 10Mbps/100Mbps. In FIFO mode, data is read and written in byte format on each positive edge of BUFRD and BUFWR. The only limitation in this mode is that BUFRD and BUFWR must be low for at least three pulses of MIICLK to be considered a valid signal. The upper layer interface can be selected according to the settings shown in Table 1. MII Interface Signals Table 2 describes the signals that provide data, status, and control to and from the MAX2986 in MII mode.
Table 1. Upper Layer Interface-Selection Pin Settings
INTERFACE MII rMII FIFO GPIO[3] 0 0 0 GPIO[6] 0 1 1 GPIO[4] 1 0 1
Table 2. MII Signal Description
NAME MIIDAT [3:0] MIITXEN LINES 4 I/O I DESCRIPTION Transmit Data. Data are transferred to the MAX2986 from the external MAC across these four lines, one nibble at a time, synchronous to MIICLK. Transmit Enable. Provides the framing for the Ethernet packet from the Ethernet MAC. This signal indicates to the MAX2986 that valid data is present on MIIDAT[3:0] and must be sampled using MIICLK. Carrier Sense. Logic-high indicates to the external host that traffic is present on the powerline and the host must wait until the signal goes invalid before sending additional data. When a packet is being transmitted, MIICRS is held high. Receive Data. Data are transferred from the MAX2986 to the external MAC across these four lines, one nibble at a time, synchronous to MIICLK. The MAX2986 properly formats the frame so the Ethernet MAC is presented with the expected preamble plus the start frame delimiter (SFD). Receive Data Valid. Logic-high indicates that the incoming data on the MIIDAT pins are valid. Receive Error. Logic-high indicates to the external MAC that the MAX2986 detected a decoding error in the receive stream. Reference Clock. A 2.5MHz (25MHz) clock in 10Mbps (100Mbps) as reference clock. Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal. Management Data Input/Output. A bidirectional signal that carries the data for the management data interface.
1
I
MIICRS
1
O
MIIDAT [7:4] MIIRXDV MIIRXER MIICLK MIIMDC MIIMDIO
4 1 1 1 1 1
O O O I I I/O
MANAGEMENT DATA UNIT
8
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Integrated Powerline Digital Transceiver
MII MAC and PHY Connections Figure 3 illustrates the connections between MAC and PHY in MII mode. Although the Tx and Rx data paths are full duplex, the MII interface is operated in halfduplex mode. MIIRXDV is never asserted at the same time as MIITXEN. On transmit, the MAX2986 asserts MIICRS some time after MIITXEN is asserted, and drops MIICRS after MIITXEN is deasserted and when the MAX2986 is ready to receive another packet. When MIICRS falls, the Ethernet MAC times out an interframe gap (IFG) (0.96s typ) and asserts MIITXEN again if there is another packet to send. This differs from the nominal behavior of MIICRS in that MIICRS can extend past the end of the packet by an arbitrary amount of time, while the MAX2986 is gaining access to the channel and transmitting the packet. MACs in 10Mbps mode do not use a jabber timeout, so there is no timing restriction on how long MIICRS can assert (other than timeouts the MAX2986 may implement). Transmissions are modulated onto the wire as soon as the transfer begins, as the MII fills the MAX2986 buffer faster than data needs to be made available to the modulator. When a packet arrives at the MAX2986, it attempts to gain access to the channel. This may not happen before the entire packet is transferred across the MII interface, so the MAX2986 buffers at least one Ethernet packet to perform this rate adaptation. On receive, when the MAX2986 anticipates that it will have a packet demodulated, it raises MIICRS to seize the half-duplex MII channel, waits a short time (an IFG), then possibly defers to MIITXEN (which may just have been asserted) plus an IFG, and then raises MIIRXDV to transfer the packet. At the end of the transfer, it drops MIICRS unless the transmit buffer is full or there is another receive packet ready to transfer. This is illustrated in Figure 4, where one receive transfer is followed by a second, which defers to MIITXEN. Data reception needs to have priority over transmission to ensure that the buffer empties faster than packets arrive off the wire. The longest the receiver needs to wait is the time to transfer one Tx frame plus an IFG or approximately 134s. However, minimum size frames can arrive at a peak rate of one every 65s, so the receive-side buffer must accommodate multiple frames (but only a little more than one Ethernet packet of data).
MAX2986
RECEIVE INCOMING MIICRS IFG MIIRXDV MIITXEN DEFER
Figure 4. Receive Defer in MII Mode
CLOCK SOURCE (2.5MHz OR 25MHz) RXCLK TXCLK TXEN RXDV ETHERNET 802.3 MAC (MII) CRS TXD[3:0] RXD[3:0] RXER MDC MDIO COL MIITXEN MIIRXDV MIICRS MIIDAT[3:0] MIIDAT[7:4] MIIRXER MIIMDC MIIMDIO BUFWR BUFRD BUFCS GND VCC MII INTERFACE MAC PHY MIICLK MAX2986
Figure 3. MAC and PHY Connection in MII Mode _______________________________________________________________________________________ 9
Integrated Powerline Digital Transceiver MAX2986
MII Signal Timing--Transmitting When a frame in the external host is ready to transmit and MIICRS is not high (the previous transmission has finished), the external host asserts MIITXEN, while data is ready on MIIDAT[3:0]. In response, the MAX2986 asserts MIICRS. While the external host keeps MIITXEN high, data is sampled synchronously with respect to MIICLK into the MAX2986 through MIIDAT. After transmission of the last byte of data and before the next positive edge of the MIICLK, MIITXEN is reset by the external host. The transmission timing of the MII interface is illustrated in Figure 5, with details in Figure 6 and Table 3.
MIICLK
MIITXEN
MIICRS
MIIDAT
DATA
DATA
DATA
DATA
Figure 5. Transmission Behavior of the MII Interface
Table 3. MII Interface--Detailed Transmit Timing*
tIH MIIDAT MIITXEN tIS MIICLK
PARAMETER tIS tIH
DESCRIPTION Setup prior to positive edge of MIICLK Hold after positive edge of MIICLK
MIN 2.5 2.5
UNITS ns ns
*Per IEEE 802.3u standard. Figure 6. MII Interface--Detailed Transmit Timing
10
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Integrated Powerline Digital Transceiver
MII Signal Timing--Receiving When a frame is ready to send from the MAX2986 to the external host, the MAX2986 asserts MIIRXDV after IFG (which is about 0.96s), while there is no transmission session in progress (with respect to MIICRS). Note: The receive process cannot start while a transmission is in progress. While the MAX2986 keeps MIIRXDV high, data is sampled synchronously with respect to MIICLK from the MAX2986 through MIIDAT. After the last byte of data is received, the MAX2986 resets MIIRXDV. Receive timing of the MII interface is illustrated in Figure 7, with details in Figure 8 and Table 4.
MAX2986
MIICLK
MIICRS IFG MIIRXDV
MIIDAT
DATA
DATA
DATA
DATA
DATA
Figure 7. Receive Behavior of the MII Interface
Table 4. MII Interface--Detailed Receive Timing*
MIIDAT MIIRXDV MIICRS tOV MIICLK tOH
PARAMETER tOV
DESCRIPTION Data valid after positive edge of MIICLK Nominal data hold time
MAX 2.5 One MIICLK period
UNITS ns
tOH
ns
*Per IEEE 802.3u standard. Figure 8. MII Interface--Detailed Receive Timing
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11
Integrated Powerline Digital Transceiver MAX2986
Reduced Media Independent Interface (rMII)
Table 5 describes the signals that provide data, status, and control to the MAX2986 in RMII mode. In this mode, data is transmitted and received in bit pairs. The rMII mode connections are shown in Figure 9. In case of an error in the received data, to eliminate the requirement for MIIRXER and still meet the requirement for undetected error rate, MIIDAT[5:4] replaces the decoded data in the receive stream with 10 until the end of carrier activity. By this replacement, the CRC check is guaranteed to detect an error and reject the packet.
Table 5. rMII Signal Description
NAME MIIDAT[1:0] DATA LINES 2 I/O I DESCRIPTION Transmit Data. Data are transferred to the interface from the external MAC across these two lines, one di-bit at a time. MIIDAT[1:0] is 00 to indicate idle when MIITXEN is deasserted. Transmit Enable. This signal indicates to the MAX2986 that valid data is present on the MIIDAT pins. MIITXEN is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented to the rMII. MII Receive Data. Data is transferred from the MAX2986 to the external MAC across these two lines, one di-bit at a time. Upon assertion of MIIRXDV, the MAX2986 ensures that MIIDAT[5:4] = 00 until proper receive decoding takes place. Receive Data Valid (CRS_DV). When asserted high, MIIRXDV indicates that the incoming data on the MIIDAT pins are valid. rMII Reference Clock. A continuous clock that provides the timing reference for MIIRXDV, MIIDAT, MIITXEN, and MIIRXER. MIICLK is sourced by the Ethernet MAC or an external source and its frequency is 5MHz (50MHz) in 10Mbps (100Mbps) data rate.
MIITXEN
1
I
MIIDAT[5:4]
2
O
MIIRXDV
1
O
MIICLK
1
I
MANAGEMENT DATA UNIT MIIMDC MIIMDIO 1 1 I I/O MII Management Data Clock. A 2.5MHz noncontinuous clock reference for the MIIMDIO signal. MII Management Data Input/Output. It is a bidirectional signal that carries the data for the management data interface.
CLOCK SOURCE (5MHz OR 50MHz) REFCLK TXEN CRS_DV ETHERNET 802.3 MAC (RMII) TXD[1:0] RXD[1:0] MDC MDIO MIICLK MIITXEN MIIRXDV MIIDAT[1:0] MIIDAT[5:4] MIIMDC MIIMDIO BUFWR BUFRD BUFCS VCC rMII INTERFACE MAC PHY MAX2986
Figure 9. MAC-PHY Connection in RMII Mode 12 ______________________________________________________________________________________
Integrated Powerline Digital Transceiver
rMII Signal Timing rMII transmit and receive timing are the same as for MII, except that the data are sent and received in 2-bit format and MIICRS is removed. FIFO Interface Signals Table 6 describes signals that provide data, status, and control to and from the MAX2986 in buffering (FIFO) mode. The FIFO buffering interface is operated in halfduplex mode. MIIRXDV is never asserted at the same time as MIITXEN, but it is able to start transmission while receive is in progress. It is highly recommended to give reception a higher priority to avoid data loss. On transmit, the MAX2986 asserts MIICRS after MIITXEN is asserted, and drops it after MIITXEN is deasserted and when the MAX2986 is ready to get another packet. When MIICRS falls, it can be asserted again if there is another packet to send. Transmissions are modulated onto the wire as soon as the transfer begins, as the interface fills the MAX2986 buffer faster than data needs to be made available to the modulator. When a packet arrives at the MAX2986, it attempts to gain access to the channel. Since this may not happen before the entire packet is transferred across the interface, the MAX2986 buffers at least one Ethernet packet to perform this rate adaptation. On receive; when the MAX2986 anticipates that it will have a packet demodulated, it raises MIIRXDV to identify the upper layer that a packet is ready to transmit. MIIRXDV drops when the last byte is transmitted. Receive direction transfers have priority over the transmit direction to ensure that the buffer empties faster than packets arrive. The minimum receive time is one Tx frame plus an IFG.
MAX2986
Table 6. FIFO Signal Description
NAME MIIDAT[7:0] DATA LINES 8 I/O I/O DESCRIPTION Transmit/Receive Data. Data are transferred to/from the MAX2986 from/to the external MAC across this bidirectional port, one byte at a time. Transmit Enable [Active High]. This signal indicates to the MAX2986 that the transmission has started, and that data on MIIDAT should be sampled using BUFWR. MIITXEN remains high to the end of the session. Transmit In Progress [Active High]. When asserted high, MIICRS indicates to the external host that outgoing traffic is present on the powerline and the host should wait until the signal goes low before sending additional data. Write [Active Low]. Inputs a write signal to the MAX2986 from the external MAC, writing the present data on MIIDAT pins into the interface buffer on each positive edge. Receive Data Valid [Active High]. When asserted high, MIIRXDV indicates that the incoming data on the MIIDAT pins are valid. Receive Error [Active High]. When asserted high, MIIRXER indicates to the external MAC that an error has occurred during the frame reception. Read [Active Low]. Inputs a read signal to the MAX2986 from the external MAC, reading the data from the MIIDAT pins of the MAX2986 on each positive edge. Chip Select [Active Low]. When asserted low, it enables the chip. Reference Clock. Used for sampling BUFWR and BUFRD.
MIITXEN
1
I
MIICRS
1
O
BUFWR MIIRXDV MIIRXER BUFRD BUFCS MIICLK
1 1 1 1 1 1
I O O I I I
______________________________________________________________________________________
13
Integrated Powerline Digital Transceiver MAX2986
FIFO Signal Timing--Transmitting When the external host is ready to transmit a frame and MIICRS is low (the previous transmission is finished), it asserts MIITXEN. The external host must assert MIITXEN if MIIRXDV is not high to avoid data loss. In response, MIICRS is asserted by the MAX2986. While the external host keeps MIITXEN high, 1 byte of data is transmitted into the MAX2986 through MIIDAT for each positive edge of BUFWR. After transmission of the last byte of data, the external host resets MIITXEN. Interactions between the external host and the MAX2986 baseband chip are shown in Figure 10. The overall transmission timing of the FIFO interface is illustrated in Figure 11 with detailed timing shown in Figure 12 and Table 7.
START
tIH MIIDAT MIITXEN tIS
NO FRAME AVAILABLE? WRITE TO THE FIFO INTERFACE
BUFWR
YES
Figure 12. FIFO Interface--Detailed Transmit Timing
1 CRS OR RXDV NO COUNTER = FRAME LENGTH
0
YES
Table 7. FIFO Interface --Transmit Timing*
PARAMETER DESCRIPTION Setup prior to positive edge of BUFWR Hold after positive edge of BUFWR TYP 3 Debounce** MIICLK +3 UNITS ns tIS
ASSERT MIITXEN
RESET MIITXEN
tIH
ns
Figure 10. Buffering Transmission Process from the External Host View
*Per IEEE 802.3u standard. **The default value of the debounce parameter is 3.
MIITXEN
MIICRS
MIIDAT
DATA
DATA
DATA
DATA
DATA
BUFWR
Figure 11. Transmission Timing of the Buffering (FIFO) Interface 14 ______________________________________________________________________________________
Integrated Powerline Digital Transceiver
FIFO Signal Timing--Receiving When a frame is ready to send from the MAX2986 to the external host, the MAX2986 asserts MIIRXDV after an IFG (which is about 0.96s), while there is no transmission session in progress (with respect to MIICRS). A receive process cannot start while a transmission is in progress. While the MAX2986 keeps MIIRXDV high, it sends 1 byte of data on MIIDAT for each positive edge on BUFRD. The first 2 bytes represent frame length in MSB-first format. After the last byte of data is received, the MAX2986 resets MIIRXDV. The direction of bidirectional data pins is controlled through BUFCS and BUFRD pins. The MAX2986 enables data output drivers when BUFCS = 0 and BUFRD = 0. The interactions between the external host and the MAX2986 baseband is shown in Figure 13 and the overall receive timing of the buffering interface is illustrated in Figure 14, with details in Figure 15 and Table 8.
MAX2986
START
MIIDAT MIIRXDV MIICRS
'0' READ LENGTH (LSB)
tOH
tOV BUFRD
MIIRXDV
'1'
READ LENGTH (MSB)
READ FROM FIFO INTERFACE
Figure 15. FIFO Interface--Detailed Receive Timing
Table 8. FIFO Interface--Receive Timing*
PARAMETER
NO COUNTER = FRAME LENGTH
DESCRIPTION Valid after negative edge of BUFRD Hold after positive edge of BUFRD
MIN Debounce** MIICLK +3 0
UNITS ns
tOV
YES
tOH
ns
Figure 13. Buffering (FIFO) Interface Receive Process from the External Host View
*Per IEEE 802.3u standard. **The default value of the debounce parameter is 3.
MIIRXDV FRAME LENGTH (LSB) MIIDAT FRAME LENGTH (MSB) DATA DATA DATA DATA
BUFRD
Figure 14. Receive Timing of the Buffering (FIFO) Interface ______________________________________________________________________________________ 15
Integrated Powerline Digital Transceiver MAX2986
Management Data Unit MDU The MIIMDIO pin is a bidirectional data pin for the management data interface. The MIIMDC signal is a clock reference for the MIIMDIO signal. The write behavior of the management data unit is illustrated in Figure 16. The read behavior of the management data unit is illustrated in Figure 17.
Ethernet Interface
The upper layer interface can be selected according to the pin settings shown in Table 9.
MIIMDC
MIIMDIO
32-BIT OPTIONAL PREAMBLE
START WRITE
5-BIT PHYSICAL ADDRESS
5-BIT REGISTER ADDRESS
TA FROM HOST
16-BIT OF DATA FROM HOST
Figure 16. Write Behavior of the Management Data Unit
MIIMDC
MIIMDIO
32-BIT OPTIONAL PREAMBLE
START READ
5-BIT PHYSICAL ADDRESS
5-BIT REGISTER ADDRESS
TA TO HOST
16-BIT OF DATA FROM HOST
Figure 17. Read Behavior of the Management Data Unit
Table 9. Upper Layer Interface-Selection Pin Settings
INTERFACE MII rMII GPIO[3] 1 1 GPIO[6] 0 0 GPIO[4] 0 1
16
______________________________________________________________________________________
Integrated Powerline Digital Transceiver
Figure 18 shows the transmit timing. tTXDV is the time that data must be valid for after a low-to-high transition on ETHTXCLK. tTXDH is the time that data must be held after a low-to-high transition on ETHTXCLK. Figure 19 shows the receive timing. tRXS is the setup time prior to the positive edge of ETHRXCLK. tRXH is the hold time after the positive edge of ETHRXCLK. For further information on the Ethernet MAC interface, refer to the IEEE 802.3 specification. shows the upper layer interface pin setting to select USB. Refer to the Universal Serial Bus Specification, Revision 1.1 for more details on the USB interface.
MAX2986
UART Interface
A serial asynchronous communication protocol using the UART standard interface is implemented in the MAX2986 baseband chip for the purpose of download/debugging MAC software. To communicate with the current MAC software, the UART interface must be configured as shown in Table 11. To download and debug HomePlug MAC software, a null modem cable is required to make a serial connection as shown in Figure 21. The MAX3221 is used as UART driver.
USB Interface
Figure 20 shows the structure of a USB cable. The two pins USBD+ and USBD- are the data pins used in the USB interface, and correspond to D+ and D- in Figure 20. VBUS is nominally +5V at the source. Figure 10
ETHTXCLK tTXDH tTXDV ETHTXEN ETHTXD[3:0] ETHTXER tTXDV < 25ns tTXDH > 5ns
MAX2986
BASEBAND UARTTXD UARTRXD
MAX3221
UART DRIVER IN OUT
DB9 CONNECTOR 1 6 2 7 3 8 4 9 5
Figure 18. Transmit Timing for Ethernet MAC Interface to the MAX2986
ETHRXCLK tRXH tRXS ETHRXD[3:0], ETHRXDV tRXS > 10ns tRXH < 10ns
Figure 21. MAX2986 UART Interface with Driver and DB9 Connector
Table 10. Upper Layer Interface-Selection Pin Settings
INTERFACE USB GPIO[3] 0 GPIO[6] 0 GPIO[4] 0
Figure 19. Receive Timing for Ethernet MAC Interface to the MAX2986
VBUS D+ DGND
VBUS D+ DGND
Table 11. UART Interface Configuration
Data Rate Data Length Stop Bit Flow Control 115,200bps 8 Bits 1 Bit None
Figure 20. USB Cable
______________________________________________________________________________________
17
Integrated Powerline Digital Transceiver MAX2986
Applications Information
Terminating Interfaces
To terminate either of the interfaces, the corresponding I/O pins should be configured as shown in Tables 12-15.
Table 12. Disabling USB Interface
LOCATION C5 B5 NAME USBDUSBD+ DIRECTION I/O I/O N.C. (no connection). TERMINATE STATUS Connect to DGND with a 5.1M resistor.
Table 13. Disabling Ethernet Interface
LOCATION L9 M4 N2 N3 M9 M7 N9 N7 M6 L5 M5 N5 M8 N8 L8 L7 M3 N4 NAME ETHTXCLK ETHRXCLK ETHCOL ETHCRS ETHTXEN ETHRXDV ETHTXER ETHRXER ETHRXD[0] ETHRXD[1] ETHRXD[2] ETHRXD[3] ETHTXD[0] ETHTXD[1] ETHTXD[2] ETHTXD[3] ETHMDC ETHMDIO DIRECTION I I I I O I O I I I I I O O O O O I/O DGND DGND DGND DGND N.C. DGND N.C. DGND DGND DGND DGND DGND N.C. N.C. N.C. N.C. N.C. N.C. TERMINATE STATUS
18
______________________________________________________________________________________
Integrated Powerline Digital Transceiver MAX2986
Table 14. Disabling MII/RMII/FIFO Interface
LOCATION K11 F11 N10 J12 K12 J13 L12 N11 N12 N13 L13 L11 H10 H12 H11 H13 J11 K13 NAME MIICRS MIITXEN MIICLK MIIDAT[7] MIIDAT[6] MIIDAT[5] MIIDAT[4] MIIDAT[3] MIIDAT[2] MIIDAT[1] MIIDAT[0] MIIRXER MIIRXDV BUFCS BUFRD BUFWR MIIMDC MIIMDIO DIRECTION O I I I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I I/O N.C. DGND DGND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD VDD VDD DGND N.C. TERMINATE STATUS
Table 15. Disabling UART
LOCATION UARTTXD UARTRXD NAME K7 L6 DIRECTION O I N.C. VDD TERMINATE STATUS
Note: Disabling the UART interface disables the MAC code update and FLASH programming features of the chip.
Interfacing the MAX2986 to the MAX2980 Analog Front End (AFE)
The interface to the MAX2980 AFE chip uses a bidirectional bus to pass the digital data to and from the DAC and ADC. Handshake lines help accomplish the data transfer as well as operation of the AFE. Figure 22 shows the interface signals. For AFE pin configuration/ description, refer to the MAX2980 data sheet.
MAX2980
AFE ADC/DAC ENREAD ENTX SHRCRV CS CLK RESETIN SHDN SCLK SDI/O SWR
MAX2986
BASEBAND AFEDAT[9:0] AFEREN AFETXEN AFEPDRX AFEFRZ AFECLK AFERESET GPIO[7] GPIO[4] GPIO[5] GPIO[6]
SI CLOCK R/W SERIAL DATA SERIAL R/W SELECT
Figure 22. MAX2980 AFE Interface to the MAX2986 ______________________________________________________________________________________ 19
Integrated Powerline Digital Transceiver MAX2986
Table 16. MAX2986 to AFE Signal Interface Description
NAME DATA LINES 1 I/O DESCRIPTION AFE Transmit Enable. The AFETXEN signal is used to enable the transmitter of the AFE. When AFETXEN and AFEREN are high, data is sent through the AFEDAD[9:0] to the DAC and then into the powerline. Setting Bus Direction. The AFEREN signal sets the direction of the data bus AFEDAD[9:0]. When high, data can be sent from the MAX2986 to the DAC in the AFE, and when low, data is sent from the ADC to the MAX2986. AFE Receiver Power-Down. When the AFE is in transmit mode, the AFEPDRX signal goes high, the receiver section of the AFE is powered down. The MAX2980 features a transmit power-saving mode that reduces current dissipation. To use this power-saving mode, lower AFEPDRX prior to the end of a transmission. If this mode is not required, connect AFEPDRX to AFETXEN and AFEREN. AFE 10-Bit ADC and DAC Bus. AFEDAD[9:0] is the 10-bit bidirectional bus that connects the MAX2986 to the AFE DAC and ADC. The direction of the bus is controlled by AFEREN described above. AFE Receive AGC Control. The AFEFRZ signal controls the AGC circuit in the receive path in the AFE. When this signal is low, the gain circuit on the input signal continuously adapts for maximum sensitivity. This signal is raised high when the MAX2986 detects a valid preamble. After the AFEFRZ signal is raised high, it continues to adapt for an additional short period of time, then it locks the currently adapted level on the incoming signal. The MAX2986 holds AFEFRZ high while receiving a transmission, and then lowers for continuous adaptation for maximum sensitivity of other incoming signals. AFE Clock. A 50MHz clock generated for the MAX2980 AFE. AFE Reset. To perform a reset on the MAX2980 AFE, AFECLK must be free running and AFERESET must be LOW for typically 1s. A reset must be performed at power-up. AFE Serial Interface Read/Write Select. AFE Serial Interface Data (Write/Read). AFE Serial Interface Clock. AFE Power-Down.
AFETXEN
O
AFEREN
1
O
AFEPDRX
1
O
AFEDAD[9:0]
10
I/O
AFEFRZ
1
O
AFECLK AFERESET GPIO[6] GPIO[5] GPIO[4] GPIO[7]
1 1 1 1 1 1
O O O I/O O O
20
______________________________________________________________________________________
Integrated Powerline Digital Transceiver
AFE Timing Figure 23 illustrates the relationship of the AFE input clock and the data into the DAC and out of the ADC. AFE Serial Interface The AFE configuration signals GPIO[4], GPIO[5], and GPIO[6] are used to program the AFE internal registers. GPIO[4] is the serial clock; GPIO[5] is the bidirectional data line for register reprogramming and reading, and when GPIO[6] is asserted HIGH, the registers are in write mode. Drive these lines low if not used. Refer to the MAX2980 data sheet for more information on the AFE serial interface timing. 2) Simple code downloaded through UART: The MAX2986 is configurable to accept code image from the UART. The first 4 bytes of the image specify the memory location in SSRAM to which the binary image should be copied (0x2020000- 0x203FFFF). The next 4 bytes specify the length of the image (excluding 8 header and 4 tail bytes), in terms of words. The specified length cannot be greater than 128kB (size of SSRAM) and must be nonzero, otherwise the boot will restart simple code downloaded through the UART after issuing an appropriate error message to the host. The last 4 bytes of image are the checksum. After the image is loaded and checksum is valid, the image is launched by jumping to the target (destination) address, otherwise, the boot restarts simple code downloaded through the UART. Five pins are used to determine the boot mode. Table 17 shows the corresponding settings (PU: pulled up, PD: pulled down, X: don't care). Pullup and pulldown resistors are 10k. GPIO[8] and GPIO[10] are two pins that are used for flash operations. These two pins are output in flash operations but they would be input in the system boot process. If an error occurs during the boot process, the error code is indicated on the LED pins: GPIO[21] (LED0_ BP0), GPIO[22] (LED1_ BP1), and GPIO[23] (LED2_BP2)
MAX2986
Upgrading and Programming MAC
There are wide ranges of boot options that provide good flexibility in running code applications on the MAX2986 through different chip interfaces. The selection of different boot modes is possible through boot pins and flash type pins, which are sensed during the MAX2986 startup process. There are two boot modes: 1) Downloading encrypted flash-resident code: The image can be downloaded into flash memory using either an I2CTM or SPITM interface. The code image address is stored at the start of flash memory. The encrypted code image in flash can be updated using TFTP protocol.
tCLK
50MHz AFE CLK
tADCO ADC DATA OUTPUT
tDACI DAC DATA INPUT
tCLK = 20ns
tADCO = 2ns
tDACI = 3ns
Figure 23. AFE ADC and DAC Timing Diagram Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SPI is a trademark of Motorola, Inc. ______________________________________________________________________________________ 21
Integrated Powerline Digital Transceiver MAX2986
according to Table 18. Pullup/pulldown resistors for LEDs are 1k or less. The states of GPIO pins and initialization pins during the boot process are shown in Table 17. See the Pin Description for more information. crystal to the MAX2986. If the external clock oscillator is used, leave XOUT unconnected as shown in Figure 25. Since the reset signal RESET is used in PLL modules, it must be activated after the PLL clock generation delay, which is about 0.5ms.
Clocks and Reset
The MAX2986 has a built-in oscillator that requires an external crystal. Use a 30MHz crystal with stability of 25ppm max over operating temperature. All other necessary clocks are generated internally by means of two integrated PLLs. Figure 24 illustrates how to connect a
GPIO Pin Usage
The MAX2986 firmware makes special use of GPIO pins as described in Table 19. GPIO pins are utilized in input, output, or both directions.
Table 17. Boot Modes
BOOT MODE FLASH TYPE Flash type is SPI (AT45DB) Flash type is SPI (SST25VF) Flash type is I2C Code downloaded through UART X BOOT/FT PINS GPIO[23] 0 1 X 0 GPIO[22] 1 1 1 0 GPIO[21] 0 0 0 0 GPIO[8] PU PU PD X GPIO[10] PU PU PU PU*
Encrypted image downloaded from flash
X = Don't care. *PU: If pin GPIO[10] is pulled down instead of pulled up, it indicates that there is no flash device connected to the chip. If this is the case and if LED0_BP0 = LED1_BP1 = 0, then the GPIO[8] line must be pulled up.
Table 18. Boot Error Codes
LED2_BP2 0 0 0 1 1 1 1 0 LED1_BP1 0 1 1 0 0 1 1 0 LED0_BP0 1 0 1 0 1 0 1 0 BOOT STATUS The flash does not contain a valid image. The size of the image is more than 128kB. The base address of the image is out of the allowed range. Checksum error. No flash is available. Invalid boot mode. No error.
22
______________________________________________________________________________________
Integrated Powerline Digital Transceiver MAX2986
CLOCK OSCILLATOR XIN 30MHz CRYSTAL 30MHz RF 1M XOUT C1 15pF C2 15pF MAX2986 N.C. XOUT OUT XIN
MAX2986
Figure 24. Connecting a Crystal to the MAX2986
Figure 25. Connecting a Clock Oscillator to the MAX2986
______________________________________________________________________________________
23
Integrated Powerline Digital Transceiver MAX2986
Table 19. GPIO Pin Usage by the MAX2986 Firmware
LOCATION C4 A5 B6 C9 B9 A9 B10 A10 B11 A11 B12 A12 A13 B4 A4 GPIO GPIO[23] GPIO[22] GPIO[21] GPIO[13] GPIO[12] GPIO[11] GPIO[10] GPIO[9] GPIO[8] GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] MAX2986 EV KIT USE HPACT_BP2 HPLINK_BP1 HPCOL_BP0 PID2 PID1 PID0 IWCS_FT1 ISDAT ISCL_FT0 PDAFE AWR_UL1 ASDAT ASCL_UL0 UL2 -- DESCRIPTION Output: Drive AFE interface activity LED Input: Boot pin 2 Output: Drive AFE interface link status LED Input: Boot pin 1 Output: Drive AFE interface collision LED Input: Boot pin 0 Output: None Input: Processor ID, bit 2 Output: None Input: Processor ID, bit 1 Output: None Input: Processor ID, bit 0 Output: Flash interface chip select Input: Nonvolatile memory bit 1 Output: Flash interface data (write) Input: Flash interface data (read) Output: Flash interface serial clock Input: Nonvolatile memory, bit 0 Output: AFE power-down Input: None Output: AFE serial interface write Input: Upper interface select, bit 1 Output: AFE serial interface data (write) Input: AFE serial interface data (read) Output: AFE serial interface clock Input: Upper layer interface select, bit 0 Output: None Input: Upper layer interface select, bit 2 Output: It is used to control external USB circuit Input: None
24
______________________________________________________________________________________
Integrated Powerline Digital Transceiver MAX2986
MAX2986 PHY/MAC 4-BIT Rx 10-BIT DATA BUS MII CONTROLLER
MAX2980 AFE DAC LINE DRIVE
ETHERNET CONNECTOR
802.3 ETHERNET MAC
4-BIT Tx
MAC
DSP
SIGNALING CONTROL
HPF ADC LPF/AGC
SIGNALING
SERIAL BUS CONTROL POWERLINE
Figure 26. Powerline Baseband to MII Application Block Diagram
MAX2986 PHY/MAC 10-BIT DATA BUS USB CONNECTOR
MAX2980 AFE DAC LINE DRIVE
USB 1.1
MAC
DSP
SIGNALING CONTROL
HPF ADC LPF/AGC
SERIAL BUS CONTROL
Figure 27. Powerline Baseband to USB Application Block Diagram
MAX2986 PHY/MAC FIFO 8-BIT DATA BUS FIFO CONTROLLER MAC DSP 10-BIT DATA BUS
MAX2980 AFE DAC LINE DRIVE
SIGNALING CONTROL
HPF ADC LPF/AGC
SIGNALING CONTROL
SERIAL BUS CONTROL
Figure 28. Powerline Baseband to FIFO Application Block Diagram ______________________________________________________________________________________ 25
Integrated Powerline Digital Transceiver MAX2986
Typical Application Circuit
MAX2986 PHY/MAC 4-BIT Rx 10-BIT DATA BUS EMBEDDED 802.3 ETHERNET MAC MAX2980 AFE DAC LINE DRIVE
ETHERNET CONNECTOR
ETHERNET PHY
4-BIT Tx
HOMEPLUG MAC
DSP
SIGNALING CONTROL
HPF ADC LPF/AGC
SIGNALING
SERIAL BUS CONTROL POWERLINE
Chip Information
PROCESS: CMOS
26
______________________________________________________________________________________
Integrated Powerline Digital Transceiver
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13
MAX2986
A
DVDD
DVSS
AVDD
GPIO[2]
GPIO[22]
VDD33
GPIO[17]
GPIO[14]
GPIO[11]
GPIO[9]
GPIO[7]
GPIO[5]
GPIO[4]
A
B
DGND
AVSS
GPIO[0]
GPIO[3]
USBD+
GPIO[21]
GPIO[18]
GPIO[15]
GPIO[12]
GPIO[10]
GPIO[8]
GPIO[6]
N.C.
B
C
VDD33
DGND
GPIO[1]
GPIO[23]
USBD-
GPIO[20]
GPIO[19]
GPIO[16]
GPIO[13]
VDD18
JTMS
JTDI
VDD33
C
D
N.C.
USBRESET
RESET
DGND
DGND
DGND
DGND
DGND
DGND
VDD18
N.C.
N.C.
N.C.
D
E
N.C.
JRTCLK
DGND
AFEFRZ
VDD18
DGND
DGND
DGND
E
F
AFETXEN
XIN
XOUT
DGND
VDD18
MIITXEN
VDD33
DGND
F
G
AFERESET
AFEDAD[0]
AFEDADI1]
AFEDAD[2]
MAX2986
VDD18
JTDO
JTRST
JTCK
G
H
AFEDAD[3]
AFEDAD[4]
AFEDAD[5]
AFEDAD[6]
MIIRXDV
BUFRD
BUFCS
BUFWR
H
J
VDD33
AFEDAD[7]
AFEDAD[8]
AFEDAD[9]
VDD18
MIIMDC
MIIDAT[7]
MIIDAT[5]
J
K
AFECLK
AFEREN
AFEPDRX
N.C.
DGND
DGND
UARTTXD
DGND
DGND
VDD18
MIICRS
MIIDAT[6]
MIIMDIO
K
L
VDD33
DVDD
DVSS
VDD33
ETHRXD[1]
UARTRXD
ETHTXD[3]
ETHTXD[2]
ETHTXCLK
VDD33
MIIRXER
MIIDAT[4]
MIIDAT[0]
L
M
AVDD
AVSS
ETHMDC
ETHRXCLK
ETHRXD[2]
ETHRXD[0]
ETHRXDV
ETHTXD[0]
ETHTXEN
DGND
DGND
N.C.
VDD33
M
N
DGND
ETHCOL
ETHCRS
ETHMDIO
ETHRXD[3]
DGND
ETHRXER
ETHTXD[1]
ETHTXER
MIICLK
MIIDAT[3]
MIIDAT[2]
MIIDAT[1]
N
1
2
3
4
5
6
7
8
9
10
11
12
13
CSBGA
______________________________________________________________________________________
27
Integrated Powerline Digital Transceiver MAX2986
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
144 BALL CSBGA.EPS
PACKAGE OUTLINE, 144 BALL CSBGA, 12x12x1.4mm, 0.8mm PITCH
21-0163
A
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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